image/svg+xml
writeEnable(1)
regDOut(0)
regDIn(0)
regDIn(1)
regDIn(2)
regDIn(15)
writeEnable(2)
writeEnable(15)
D
Q
En
Reg0
D
Q
En
Reg1
regDOut(1)
0
1
0
1
dIn
clk
D
Q
En
Reg2
regDOut(2)
D
Q
En
Reg15
regDOut(15)
0
1
writeEnable(0)
AddressDecoder
add
mode0
mode1
enable
OutputMux
shiftLoadSel
shiftSetEnable
globalWriteEnable
dOut
shiftOut
Mode00011011
FunctionLUTShiftRegRAMSet/Reset
FunctionGenerator
dIn
clk
add(0)
mode(0)
mode(1)
enable
dOut
shiftOut
add(1)
add(2)
add(3)
8 Inputs
2 Outputs
mode0
mode1
enable
shiftLoadSel
shiftSetEnable
globalWriteEnable
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
X
1
1
1
1
0
1
0
0
1
1
1
0
1
0
LUT
ShiftReg
RAM
Set/Reset
shiftLoadSel
shiftSetEnable
globalWriteEnable