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-- RISA Project
-- Author: A.Greensted
-- Module:
-- Description:
-- History:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library SnapLib;
use SnapLib.SnapPkg.all;

entity WorkingRegisters is
	port (	clk			: in		std_logic;
				enable		: in		std_logic;

				portADIn		: in		std_logic_vector(15 downto 0);

				portAWEn		: in		std_logic;

				portAAdd		: in		std_logic_vector(4 downto 0);
				portBAdd		: in		std_logic_vector(4 downto 0);

				portADOut	: out		std_logic_vector(15 downto 0);
				portBDOut	: out		std_logic_vector(15 downto 0));

end WorkingRegisters;

architecture General of WorkingRegisters is
	
	-- Create Reg file address type
	subtype REG_FILE_ADD_TYPE is integer range 0 to 31;

	-- Create types for reg file
	subtype regType is std_logic_vector(15 downto 0);
	type REG_FILE_TYPE is array(31 downto 0) of regType;

	-- Declare regFile
	signal regFile : REG_FILE_TYPE; -- := (others => x"0000");

begin


PortAWrite : process(clk)
	variable writeAAdd : REG_FILE_ADD_TYPE;
begin

	if (clk'event and clk='1') then

		if (enable = '1' and portAWEn = '1') then
			writeAAdd := to_integer(unsigned(portAAdd));
			regFile(writeAAdd) <= portADIn;

		end if;

	end if;

end process;


PortARead : process(portAAdd, regFile)
	variable readAAdd : REG_FILE_ADD_TYPE;
begin

	readAAdd := to_integer(unsigned(portAAdd));
	portADOut <= regFile(readAAdd);

end process;


PortBRead : process(portBAdd, regFile)
	variable readBAdd : REG_FILE_ADD_TYPE;
begin

	readBAdd := to_integer(unsigned(portBAdd));
	portBDOut <= regFile(readBAdd);

end process;


end General;