---------------------------------------------------------------------------------------------------------------
-- RISA Project
-- Author: A.Greensted
-- Module:
-- Description:
-- History:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library SnapLib;
use SnapLib.SnapPkg.all;

entity SnapLinkTx is
	port (	clk					: in		std_logic;
				enable				: in		std_logic;
				nReset				: in		std_logic;

				sampleEn				: in		std_logic;
				txReset				: in		std_logic;

				dataBits				: in		SNAPTYPE_SNAPLINK_DATABITS;

				sendData				: in		std_logic;
				txData				: in		std_logic_vector(17 downto 0);
				txBusy				: out		std_logic;

				serialTxOut			: out		std_logic);

end SnapLinkTx;

architecture General of SnapLinkTx is

	type TX_STATES is (IDLE, TX_WAIT, TX_START_BIT, TX_DATA, TX_PARITY, TX_STOP_BIT);
	signal state		: TX_STATES;

	signal parityBit	: std_logic;
	signal bitCount	: unsigned(4 downto 0);
	signal dataReg		: std_logic_vector(17 downto 0);

	signal runCounter	: std_logic;
	signal delayCount	: unsigned(2 downto 0);
	signal nextBit		: std_logic;

	signal busy			: std_logic;

begin

txBusy <= busy;

-- DelayCounter -----------------------------------------------------------------------------------------------
-- Times the delay between packet bits (8 sampleEn pulses)
---------------------------------------------------------------------------------------------------------------
DelayCounter : process (clk)
begin

	if (clk'event and clk = '1') then

		if (nReset='0') then
			delayCount <= b"000";

		elsif (enable='1') then

			if (runCounter = '0' or txReset='1') then
				delayCount <= b"000";

			elsif (sampleEn = '1') then
				delayCount <= delayCount + 1;

			end if;
		end if;
	end if;

end process DelayCounter;

nextBit <= '1' when (delayCount=b"111" and sampleEn='1' and runCounter='1') else '0';

-- StateDecode ------------------------------------------------------------------------------------------------
-- Generates various signals that are derived from the state machine's state
---------------------------------------------------------------------------------------------------------------
StateDecode : process(state, dataReg, parityBit)
begin
	case state is
		when IDLE			=> serialTxOut <= '1';
									runCounter	<= '0';

		when TX_WAIT		=> serialTxOut <= '1';
									runCounter	<= '0';

		when TX_START_BIT	=> serialTxOut <= '0';
									runCounter	<= '1';

		when TX_DATA		=> serialTxOut <= dataReg(0);
									runCounter	<= '1';

		when TX_PARITY		=> serialTxOut <= parityBit;
									runCounter	<= '1';

		when TX_STOP_BIT	=> serialTxOut <= '1';
									runCounter	<= '1';
	end case;
end process StateDecode;

-- StateMachine -----------------------------------------------------------------------------------------------
-- State machine controlling the receiving process
---------------------------------------------------------------------------------------------------------------
StateMachine: process (clk)
begin

	if (clk'event and clk='1') then

		if (nReset='0') then
			parityBit	<= '0';
			bitCount		<= (others => '0');
			dataReg		<= (others => '0');
			busy			<= '0';
			state			<= IDLE;

		elsif (enable='1') then

			if (txReset='1') then
				parityBit	<= '0';
				bitCount		<= (others => '0');
				dataReg		<= (others => '0');
				busy			<= '0';
				state			<= IDLE;

			else
				case state is

					when IDLE =>
						parityBit <= '0';

						case dataBits is
							when SNAP_SNAPLINK_16DATABITS	=> bitCount <= "01111";
							when SNAP_SNAPLINK_17DATABITS	=> bitCount <= "10000";
							when SNAP_SNAPLINK_18DATABITS	=> bitCount <= "10001";
						end case;

						if (sendData='1') then
							dataReg	<= txData;
							busy		<= '1';

							if (sampleEn='1') then
								state <= TX_START_BIT;
							else
								state <= TX_WAIT;
							end if;

						else
							busy <= '0';

						end if;


					when TX_WAIT =>
						if (sampleEn='1') then
							state <= TX_START_BIT;
						end if;


					when TX_START_BIT =>
						if (nextBit='1') then
							state <= TX_DATA;
						end if;


					when TX_DATA =>
						if (nextBit='1') then
							parityBit	<= parityBit xor dataReg(0);
							dataReg		<= '1' & dataReg(17 downto 1);
							bitCount		<= bitCount - 1;

							if (bitCount="00000") then
								state <= TX_PARITY;
							end if;

						end if;


					when TX_PARITY =>
						if (nextBit='1') then
							state <= TX_STOP_BIT;
						end if;


					when TX_STOP_BIT =>
						if (nextBit='1') then
							state <= IDLE;
						end if;

				end case;

			end if;

		end if;

	end if;

end process StateMachine;

end General;