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-- RISA Project
-- Author: A.Greensted
-- Module:
-- Description:
-- History:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library SnapLib;
use SnapLib.SnapPkg.all;

entity ProgramCounter is
	port (	clk			: in		std_logic;
				enable		: in		std_logic;
				nReset		: in		std_logic;
				
				dIn			: in		std_logic_vector(SNAPTYPE_MEM_ADD'range);

				isrBranchEn	: in		std_logic;
				pcWEn			: in		std_logic;
				pcOut			: out		SNAPTYPE_MEM_ADD;

				activePC		: in		SNAPTYPE_MEM_ADD;

				braPCWEn		: in		std_logic;
				braPCOut		: out		SNAPTYPE_MEM_ADD;

				isrPCWEn		: in		std_logic;
				isrPCOut		: out		SNAPTYPE_MEM_ADD);

end ProgramCounter;

architecture General of ProgramCounter is

	signal countEn		: std_logic;
	signal count		: unsigned(SNAPTYPE_MEM_ADD'range);

begin

pcOut		<= std_logic_vector(count);

Divider : process(clk)
begin

	if (clk'event and clk='1') then
		
		if (nReset='0') then
			countEn <= '0';

		elsif (enable='1') then

			countEn <= not countEn;

		end if;

	end if;

end process;


PCControl : process(clk)
begin

	if (clk'event and clk='1') then
		
		if (nReset='0') then
			count <= (others => '0');

		elsif (enable='1') then

			if (isrBranchEn='1') then
				count <= unsigned(SNAP_ISR_ADD);

			elsif (pcWEn='1') then
				count <= unsigned(dIn);

			elsif (countEn='1') then
				count <= count + 2;

			end if;

		end if;

	end if;

end process;

TrapControl : process(clk)
	variable braPC : SNAPTYPE_MEM_ADD;
	variable isrPC : SNAPTYPE_MEM_ADD;
begin

	if (clk'event and clk='1') then
		
		if (nReset='0') then
			braPC := (others => '0');
			isrPC := (others => '0');

		elsif (enable='1') then

			if (braPCWEn='1') then
				braPC := activePC;

			end if;

			if (isrPCWEn='1') then
				isrPC := activePC;

			end if;

		end if;

	end if;

	braPCOut <= braPC;
	isrPCOut <= isrPC;

end process;

end General;