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-- RISA Project
-- Author: A.Greensted
-- Module: IOPort	
-- Description: A simple data IO port, with data output enable bits
-- History:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library CommonLib;
use CommonLib.CommonPkg.all;

entity IOPort is
	port (	clk					: in		std_logic;
				enable				: in		std_logic;
				nReset				: in		std_logic;

				dIn					: in		std_logic_vector(7 downto 0);

				dataRegWEn			: in		std_logic;									-- Data write to port
				dataRegOut			: out		std_logic_vector(7 downto 0);			-- Data read from port

				dataOutEnWEn		: in		std_logic;
				dataOutEnOut		: out		std_logic_vector(7 downto 0);
				
				ioPortDIn			: in		std_logic_vector(7 downto 0);
				ioPortOutEn			: out		std_logic_vector(7 downto 0);
				ioPortDOut			: out		std_logic_vector(7 downto 0));
end IOPort;

architecture General of IOPort is

	signal dataReg				: std_logic_vector(7 downto 0);
	signal outEnReg			: std_logic_vector(7 downto 0);

begin

ioPortDOut	<= dataReg;
dataRegOut	<= ioPortDIn;

dataOutEnOut	<= outEnReg;
ioPortOutEn		<= outEnReg;

-- RegWriteControl -------------------------------------------------------------------------------------------
-- Controls writing to IO Port Registers
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RegWriteControl : process(clk)
begin
	if (clk'event and clk='1') then

		if (nReset='0') then
			dataReg	<= (others => '0');
			outEnReg	<= (others => '0');

		elsif (enable='1') then

			-- Data Reg Write
			if (dataRegWEn='1') then
				dataReg <= dIn;
			end if;

			-- Direction Reg Write
			if (dataOutEnWEn='1') then
				outEnReg <= dIn;
			end if;

		end if;

	end if;

end process RegWriteControl;

end General;