---------------------------------------------------------------------------------------------------------------
-- RISA Project
-- Author: A.Greensted
-- Module:
-- Description:
-- History:
---------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library ConfigLib;
use ConfigLib.ConfigPkg.all;

library FPGALib;
use FPGALib.FPGAPkg.all;

entity FunctionUnit is
	port (	clk					: in		std_logic;
				nReset				: in		std_logic;

				fDIn					: in		std_logic;
				mode					: in		std_logic_vector(1 downto 0);
				enable				: in		std_logic;

				dIn					: in		std_logic_vector(3 downto 0);

				muxSel				: in		std_logic;
				muxDIn				: in		std_logic_vector(1 downto 0);

				regDIn				: in		std_logic;
				regEn					: in		std_logic;
				regSet				: in		std_logic;
				regReset				: in		std_logic;

				fDOut					: out		std_logic;
				muxDOut				: out		std_logic;
				regDOut				: out		std_logic;

				shChnIn				: in		std_logic;
				shChnOut				: out		std_logic;
				cyChnIn				: in		std_logic;
				cyChnOut				: out		std_logic;

				cnfChnDIn			: in		std_logic;
				cnfChnDOut			: out		std_logic;
				cnfChnShiftEn		: in		std_logic;
				cnfChnLoadEn		: in		std_logic;
				cnfChnReadBackEn	: in		std_logic);

end FunctionUnit;

architecture General of FunctionUnit is

	signal fgDIn			: std_logic;
	signal fgMode			: std_logic_vector(1 downto 0);
	signal fgEnable		: std_logic;
	signal fgDOut			: std_logic;

	signal abMuxOut		: std_logic;
	signal muxS1			: std_logic;
	signal carryInject	: std_logic;
	signal bigMuxOut		: std_logic;
	signal carry			: std_logic;

	signal muxS				: std_logic;
	signal muxA				: std_logic;
	signal muxB				: std_logic;

	signal muxOut			: std_logic;

	signal regD				: std_logic;
	signal regE				: std_logic;
	signal regS				: std_logic;
	signal regR				: std_logic;
	signal regOut			: std_logic;

	signal cnfBit			: std_logic_vector(0 to 20);
	signal cnfChn			: std_logic_vector(0 to 21);

	signal fgCnfChnDIn	: std_logic;
	signal fgCnfChnDOut	: std_logic;
	signal regCnfChnDIn	: std_logic;
	signal regCnfChnDOut	: std_logic;

begin

-- ConfigChain ----------------------------------------------------------------------------------------------
-- Create a configuration chain
-------------------------------------------------------------------------------------------------------------
CnfBitGeneration : for b in 0 to 20 generate
begin
	FUCnfBit : ConfigurableBit
	port map (	clk					=> clk,
					nReset				=> nReset,
					cnfBit				=> cnfBit(b),
					cnfChnDIn			=> cnfChn(b),
					cnfChnDOut			=> cnfChn(b+1),
					cnfChnShiftEn		=> cnfChnShiftEn,
					cnfChnLoadEn		=> cnfChnLoadEn,
					cnfChnReadBackEn	=> cnfChnReadBackEn);
end generate;

cnfChn(0) <= cnfChnDIn;
regCnfChnDIn <= cnfChn(21);
fgCnfChnDIn <= regCnfChnDOut;
cnfChnDOut <= fgCnfChnDOut;


-- DInSelect ------------------------------------------------------------------------------------------------
-- Select the data input for the Function Generator
-------------------------------------------------------------------------------------------------------------
DInSelect : process(fDIn, shChnIn, cnfBit)
	variable data : std_logic;
begin

	if (cnfBit(0) = '1') then
		data := fDIn;
	else
		data := shChnIn;
	end if;

	if (cnfBit(1) = '1') then
		data := not data;
	end if;

	fgDIn <= data;

end process;

-- Inverters ------------------------------------------------------------------------------------------------
-- Configurable signal inversions
-------------------------------------------------------------------------------------------------------------
fgMode(0)	<= not mode(0)		when (cnfBit(2)='1')		else mode(0);
fgMode(1)	<= not mode(1)		when (cnfBit(3)='1')		else mode(1);
fgEnable		<= not enable		when (cnfBit(4)='1')		else enable;

muxS1			<= not dIn(3)		when (cnfBit(5)='1')		else dIn(3);
carryInject	<= not dIn(2)		when (cnfBit(6)='1')		else dIn(2);

muxS			<= not muxSel		when (cnfBit(8)='1')		else muxSel;
muxA			<= not muxDIn(0)	when (cnfBit(10)='1')	else muxDIn(0);
muxB			<= not muxDIn(1)	when (cnfBit(11)='1')	else muxDIn(1);

regE			<= not regEn		when (cnfBit(18)='1')	else regEn;
regS			<= not regSet		when (cnfBit(19)='1')	else regSet;
regR			<= not regReset	when (cnfBit(20)='1')	else regReset;

-- FuncGen --------------------------------------------------------------------------------------------------
-- The Function Units Function Generator
-------------------------------------------------------------------------------------------------------------
FuncGen : FunctionGenerator
port map (	clk					=> clk,
				nReset				=> nReset,
				dIn					=> fgDIn,
				mode					=> fgMode,
				enable				=> fgEnable,
				add					=> dIn,
				shiftOut				=> shChnOut,
				dOut					=> fgDOut,
				cnfChnDIn			=> fgCnfChnDIn,
				cnfChnDOut			=> fgCnfChnDOut,
				cnfChnShiftEn		=> cnfChnShiftEn,
				cnfChnLoadEn		=> cnfChnLoadEn,
				cnfChnReadBackEn	=> cnfChnReadBackEn);

ABMux :		abMuxOut		<= (dIn(1) and dIn(0))	when (cnfBit(7)='1')		else dIn(0);
BigMux :		bigMuxOut	<= muxOut					when (muxS1='1')			else fgDOut;
carryMux :	carry			<= cyChnIn					when (cnfBit(13)='1')	else carryInject;

-- ExtMux ---------------------------------------------------------------------------------------------------
-- The Extension Mux, used seperately, or as part of the 4 input big mux
-------------------------------------------------------------------------------------------------------------
ExtMux : process (carryInject, muxS, muxA, muxB, cnfBit)
	variable sel : std_logic;
begin
	if (cnfBit(9)='1') then
		sel := muxS;
	else
		sel := carryInject;
	end if;

	if (sel='1') then
		muxOut <= muxB;
	else
		muxOut <= muxA;
	end if;

end process;

muxDOut <= muxOut;


-- CySelect -------------------------------------------------------------------------------------------------
-- Selects the carry chain input and output
-------------------------------------------------------------------------------------------------------------
CySelect : process(fgDOut, cnfBit, abMuxOut, carry)
begin

	if (cnfBit(12)='1' or fgDOut='1') then
		cyChnOut <= carry;
	else
		cyChnOut <= abMuxOut;
	end if;

end process;


-- FOutSelect -----------------------------------------------------------------------------------------------
-- Selects the Function Units combinatorial output
-------------------------------------------------------------------------------------------------------------
FOutSelect : process(fgDOut, carry, bigMuxOut, cnfBit)
	variable data : std_logic;
begin

	if (cnfBit(14)='1') then
		data := fgDOut xor carry;
	else
		data := fgDOut;
	end if;

	if (cnfBit(15)='1') then
		fDOut <= bigMuxOut;
	else
		fDOut <= data;
	end if;

end process;

-- RegDInSelect ---------------------------------------------------------------------------------------------
-- Selects the Register's data input
-------------------------------------------------------------------------------------------------------------
RegDInSelect : process (regDIn, regOut, cnfBit)
begin

	if (cnfBit(17)='1') then
		regD <= not regOut;
	else
		if (cnfBit(16)='1') then
			regD <= not regDIn;
		else
			regD <= regDIn;
		end if;
	end if;

end process;

-- ConfigReg -----------------------------------------------------------------------------------------------
-- A Configurable Set Reset Register
-------------------------------------------------------------------------------------------------------------
ConfigReg : ConfigurableSRRegister
port map (	clk					=> clk,
				nReset				=>	nReset,
				d						=> regD,
				en						=> regE,
				s						=> regS,
				r						=> regR,
				q						=> regOut,
				cnfChnDIn			=> regCnfChnDIn,
				cnfChnDOut			=> regCnfChnDOut,
				cnfChnShiftEn		=> cnfChnShiftEn,
				cnfChnLoadEn		=> cnfChnLoadEn,
				cnfChnReadBackEn	=> cnfChnReadBackEn);

regDOut <= regOut;

end General;