---------------------------------------------------------------------------------------------------------------
-- RISA Project
-- Author: A.Greensted
-- Module:
-- Description:
-- History:
---------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library ConfigLib;
use ConfigLib.ConfigPkg.all;

entity FunctionGenerator is
	port (	clk					: in		std_logic;
				nReset				: in		std_logic;

				dIn					: in		std_logic;
				mode					: in		std_logic_vector(1 downto 0);
				enable				: in		std_logic;

				add					: in		std_logic_vector(3 downto 0);

				shiftOut				: out		std_logic;
				dOut					: out		std_logic;
				
				cnfChnDIn			: in		std_logic;
				cnfChnDOut			: out		std_logic;
				cnfChnShiftEn		: in		std_logic;
				cnfChnLoadEn		: in		std_logic;
				cnfChnReadBackEn	: in		std_logic);

end FunctionGenerator;

architecture General of FunctionGenerator is

	signal globalWriteEnable	: std_logic;
	signal shiftSetEnable		: std_logic;
	signal shiftLoadSel			: std_logic;

	signal writeEnable			: std_logic_vector(15 downto 0);			-- Register write enable signals
	signal regDIn					: std_logic_vector(15 downto 0);			-- Register input data signal
	signal regDOut					: std_logic_vector(15 downto 0);			-- Register output data signal

	signal cnfChn					: std_logic_vector(16 downto 0);			-- Internal configuration chain

begin

globalWriteEnable	<= enable and mode(1) and (not mode(0));
shiftSetEnable		<= enable and mode(0);
shiftLoadSel		<= enable and (not mode(1)) and mode(0);

-- Connect ends of internal conf chain to cnfIn and cnfOut
cnfChn(0)	<= cnfChnDIn;
cnfChnDOut	<= cnfChn(16);

shiftOut <= regDOut(15);	-- Shift out connects directly to the output of the 15th (last) register


-- AddressDecoder -------------------------------------------------------------------------------------------
-- Decodes the add bus into the writeEnable signals
-------------------------------------------------------------------------------------------------------------
AddressDecoder : process (add)
begin

	case add is
		when "0000"		=> writeEnable <= b"0000_0000_0000_0001";
		when "0001"		=> writeEnable <= b"0000_0000_0000_0010";
		when "0010"		=> writeEnable <= b"0000_0000_0000_0100";
		when "0011"		=> writeEnable <= b"0000_0000_0000_1000";

		when "0100"		=> writeEnable <= b"0000_0000_0001_0000";
		when "0101"		=> writeEnable <= b"0000_0000_0010_0000";
		when "0110"		=> writeEnable <= b"0000_0000_0100_0000";
		when "0111"		=> writeEnable <= b"0000_0000_1000_0000";

		when "1000"		=> writeEnable <= b"0000_0001_0000_0000";
		when "1001"		=> writeEnable <= b"0000_0010_0000_0000";
		when "1010"		=> writeEnable <= b"0000_0100_0000_0000";
		when "1011"		=> writeEnable <= b"0000_1000_0000_0000";

		when "1100"		=> writeEnable <= b"0001_0000_0000_0000";
		when "1101"		=> writeEnable <= b"0010_0000_0000_0000";
		when "1110"		=> writeEnable <= b"0100_0000_0000_0000";
		when "1111"		=> writeEnable <= b"1000_0000_0000_0000";

		when others		=> writeEnable <= "UUUUUUUUUUUUUUUU";
	end case;

end process AddressDecoder;

-- RegDInGenerate -------------------------------------------------------------------------------------------
-- Actuacl register instatiation
-------------------------------------------------------------------------------------------------------------
regDIn(0) <= dIn;

DInGenerate : for i in 1 to 15 generate
begin

	process (shiftLoadSel, dIn, regDOut)
	begin
		if (shiftLoadSel='1') then
			regDIn(i) <= regDOut(i-1);
		else
			regDIn(i) <= dIn;
		end if;
	end process;

end generate DInGenerate;

-- RegInstantiate -------------------------------------------------------------------------------------------
-- Actuacl register instatiation
-------------------------------------------------------------------------------------------------------------
RegInstantiate : for i in 0 to 15 generate
	signal enable : std_logic;
begin

	enable <= (writeEnable(i) and globalWriteEnable) or shiftSetEnable;

	FPCnfReg : ConfigurableRegister
	port map( 	clk					=> clk,
					nReset				=> nReset,

					d						=> regDIn(i),
					en						=> enable,
					q						=> regDOut(i),

					-- Config Chain
					cnfChnDIn			=> cnfChn(i),
					cnfChnDOut			=> cnfChn(i+1),
					cnfChnShiftEn		=> cnfChnShiftEn,
					cnfChnLoadEn		=> cnfChnLoadEn,
					cnfChnReadBackEn	=> cnfChnReadBackEn);

end generate RegInstantiate;


-- ReadAddressDecoder ---------------------------------------------------------------------------------------
-- Decodes the writeAdd bus into the writeEnable signals
-------------------------------------------------------------------------------------------------------------
ReadAddressDecoder : process (add, regDOut)
begin

	case add is
		when "0000"		=> dOut <= regDOut(0);
		when "0001"		=> dOut <= regDOut(1);
		when "0010"		=> dOut <= regDOut(2);
		when "0011"		=> dOut <= regDOut(3);

		when "0100"		=> dOut <= regDOut(4);
		when "0101"		=> dOut <= regDOut(5);
		when "0110"		=> dOut <= regDOut(6);
		when "0111"		=> dOut <= regDOut(7);

		when "1000"		=> dOut <= regDOut(8);
		when "1001"		=> dOut <= regDOut(9);
		when "1010"		=> dOut <= regDOut(10);
		when "1011"		=> dOut <= regDOut(11);

		when "1100"		=> dOut <= regDOut(12);
		when "1101"		=> dOut <= regDOut(13);
		when "1110"		=> dOut <= regDOut(14);
		when "1111"		=> dOut <= regDOut(15);

		when others		=> dOut <= 'U';
	end case;

end process ReadAddressDecoder;

end General;