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-- RISA Project
-- Author: A.Greensted
-- Module: RafbricIOPort	
-- Description: An IO port for connecting to the FPGA fabric
-- History:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library CommonLib;
use CommonLib.CommonPkg.all;

entity FabricIOPort is
	port (	clk					: in		std_logic;
				enable				: in		std_logic;
				nReset				: in		std_logic;

				dIn					: in		std_logic_vector(5 downto 0);

				dataRegWEn			: in		std_logic;								-- Data write to fabric
				dataRegOut			: out		std_logic_vector(5 downto 0);		-- Data read from fabric

				ioPortDIn			: in		std_logic_vector(5 downto 0);		-- Data from fabric
				ioPortDOut			: out		std_logic_vector(5 downto 0));	-- Data to fabric
end FabricIOPort;

architecture General of FabricIOPort is

	signal dataReg : std_logic_vector(5 downto 0);

begin

ioPortDOut	<= dataReg;
dataRegOut	<= ioPortDIn;

-- RegWriteControl -------------------------------------------------------------------------------------------
-- Controls writing to IO Port Registers
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RegWriteControl : process(clk)
begin
	if (clk'event and clk='1') then

		if (nReset='0') then
			dataReg	<= (others => '0');

		elsif (enable='1') then

			-- Data Reg Write
			if (dataRegWEn='1') then
				dataReg <= dIn;
			end if;

		end if;

	end if;

end process RegWriteControl;

end General;