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-- RISA Project
-- Author: A.Greensted
-- Module:
-- Description:
-- History:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library ConfigLib;
use ConfigLib.ConfigPkg.all;

entity FabricCAP is
		port (	clk						: in		std_logic;
					enable					: in		std_logic;
					nReset					: in		std_logic;

					dIn						: in		std_logic_vector(15 downto 0);

					controlRegWEn			: in		std_logic;
					controlRegOut			: out		std_logic_vector(15 downto 0);

					dataRegWEn				: in		std_logic;
					dataRegOut				: out		std_logic_vector(15 downto 0);

					cnfChainLockRequest	: out		std_logic;
					cnfChainLock			: in 		std_logic;
					cnfChainShiftEn		: out		std_logic;
					cnfChainLoadEn			: out		std_logic;
					cnfChainReadBackEn	: out		std_logic;

					cnfChainOut				: out		std_logic;
					cnfChainIn				: in		std_logic;

					selChainLockRequest	: out 	std_logic;
					selChainLock			: in 		std_logic;
					selChainShiftEn		: out		std_logic;
					selChainFeedbackEn	: out		std_logic;

					selChainOut				: out		std_logic;
					selChainIn				: in		std_logic);

end FabricCAP;

architecture General of FabricCAP is

	type STATES is (IDLE, DATA_XFER);
	signal state				: STATES;

	signal dataBits			: std_logic_vector(3 downto 0);
	signal chainSelection	: CONFIGTYPE_CHAIN;
	signal linkBusy			: std_logic;
	signal feedbackEn			: std_logic;
	signal linkReset			: std_logic;

	signal bitCount			: unsigned(3 downto 0);
	signal dataReg				: std_logic_vector(15 downto 0);

	signal chainDIn			: std_logic;

begin

controlRegOut(15 downto 12)	<= dataBits;								-- Data Bits
controlRegOut(11 downto 8)		<= (others => '0');
controlRegOut(7)					<= selChainLock;							-- Selection Chain Lock
controlRegOut(6)					<= cnfChainLock;							-- Configuration Chain Lock
controlRegOut(5)					<= to_std_logic(chainSelection);		-- Chain Selection
controlRegOut(4)					<= linkBusy;								-- Chain Busy (reading/writing data)
controlRegOut(3)					<= feedbackEn;								-- Selection Chain Feedback enabled
controlRegOut(2 downto 0)		<= (others => '0');						-- readBackEn, loadEn and reset all read as '0'

dataRegOut <= dataReg;

cnfChainOut <= dataReg(15);
selChainOut <= dataReg(15);

selChainFeedbackEn <= feedbackEn;

RegWriteControl : process(clk)
begin
	if (clk'event and clk='1') then

		selChainLockRequest	<= '0';
		cnfChainLockRequest	<= '0';
		cnfChainReadBackEn	<= '0';
		cnfChainLoadEn			<= '0';
		linkReset				<= '0'; -- reset this to zero

		if (nReset='0') then
			dataBits					<= b"1111";
			chainSelection			<= CONFIG_SEL_CHAIN;
			feedbackEn				<=	'0';

		elsif (enable='1') then

			-- Control Reg Write
			if (controlRegWEn = '1') then

				if (dIn(0)='1') then						--- Can perform a link Reset even when the link is busy
					linkReset				<= '1';

				elsif (linkBusy='0') then
					dataBits					<= dIn(15 downto 12);
					selChainLockRequest	<= dIn(7);
					cnfChainLockRequest	<= dIn(6);
					chainSelection			<= to_CONFIGTYPE_CHAIN(dIn(5));
					feedbackEn				<=	dIn(3);
					cnfChainReadBackEn	<= dIn(2);
					cnfChainLoadEn			<= dIn(1);
					linkReset				<= '0';

				end if;

			end if;

		end if;

	end if;

end process RegWriteControl;


-- StateDecode ------------------------------------------------------------------------------------------------
-- Generates various signals that are derived from the state machine's state
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StateDecode : process(chainSelection, selChainIn, cnfChainIn, state)
begin

	case chainSelection is
		when CONFIG_SEL_CHAIN =>	chainDIn <= selChainIn;
		when CONFIG_CNF_CHAIN =>	chainDIn <= cnfChainIn;
	end case;

	cnfChainShiftEn <= '0';
	selChainShiftEn <= '0';

	if (state=DATA_XFER) then
		case chainSelection is
			when CONFIG_SEL_CHAIN =>	selChainShiftEn <= '1';
			when CONFIG_CNF_CHAIN =>	cnfChainShiftEn <= '1';
		end case;
	end if;

end process StateDecode;


-- StateMachine -----------------------------------------------------------------------------------------------
-- State machine controlling the chain writting and reading process
---------------------------------------------------------------------------------------------------------------
StateMachine: process (clk)
begin

	if (clk'event and clk = '1') then

		if (nReset='0') then
			bitCount		<= (others => '0');
			dataReg		<= (others => '0');
			linkBusy		<= '0';
			state			<= IDLE;

		elsif (enable='1') then

			if (linkReset = '1') then
				bitCount		<= (others => '0');
				dataReg		<= (others => '0');
				linkBusy		<= '0';
				state			<= IDLE;

			else
				case state is

					when IDLE =>
						bitCount <= unsigned(dataBits);

						if (dataRegWEn='1') then
							dataReg	<= dIn;
							linkBusy	<= '1';
							state		<= DATA_XFER;

						else
							linkBusy <= '0';

						end if;

					when DATA_XFER =>
						bitCount	<= bitCount - 1;
						dataReg	<= dataReg(14 downto 0) & chainDIn;

						if (bitCount="0000") then
							state <= IDLE;
						end if;

				end case;

			end if;
		end if;
	end if;

end process StateMachine;

end General;