---------------------------------------------------------------------------------------------------------------
-- RISA Project
-- Author: A.Greensted
-- Module:
-- Description:
-- History:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package FPGAPkg is

	type FPGATYPE_LOGIC_DIR	is (	FPGA_NORTH,
											FPGA_SOUTH,
											FPGA_EAST,
											FPGA_WEST);

	type FPGATYPE_CLUSTER_OUTPUTS is record
		-- Chains
		shChnOut_N			: std_logic;
		cyChnOut_N			: std_logic;
		shChnOut_S			: std_logic;
		cyChnOut_S			: std_logic;
		shChnOut_E			: std_logic;
		cyChnOut_E			: std_logic;
		shChnOut_W			: std_logic;
		cyChnOut_W			: std_logic;
		-- Register Links
		linkROut_N			: std_logic_vector(1 downto 0);
		linkROut_S			: std_logic_vector(1 downto 0);
		linkROut_E			: std_logic_vector(1 downto 0);
		linkROut_W			: std_logic_vector(1 downto 0);
		-- Combinatorial Links
		linkCOut_N			: std_logic;
		linkCOut_S			: std_logic;
		linkCOut_E			: std_logic;
		linkCOut_W			: std_logic;
	end record FPGATYPE_CLUSTER_OUTPUTS;


	type FPGATYPE_IOBLOCK_OUTPUTS is record
		-- Pads
		linkPAOut			: std_logic;
		linkPBOut			: std_logic;
		linkIOOut			: std_logic_vector(4 downto 0);
		-- Chains
		shChnOut				: std_logic;
		cyChnOut				: std_logic;
	end record FPGATYPE_IOBLOCK_OUTPUTS;


	component FunctionGenerator is
		port (	clk					: in		std_logic;
					nReset				: in		std_logic;
					dIn					: in		std_logic;
					mode					: in		std_logic_vector(1 downto 0);
					enable				: in		std_logic;
					add					: in		std_logic_vector(3 downto 0);
					shiftOut				: out		std_logic;
					dOut					: out		std_logic;
					cnfChnDIn			: in		std_logic;
					cnfChnDOut			: out		std_logic;
					cnfChnShiftEn		: in		std_logic;
					cnfChnLoadEn		: in		std_logic;
					cnfChnReadBackEn	: in		std_logic);
	end component;

	component FunctionUnit is
		port (	clk					: in		std_logic;
					nReset				: in		std_logic;
					fDIn					: in		std_logic;
					mode					: in		std_logic_vector(1 downto 0);
					enable				: in		std_logic;
					dIn					: in		std_logic_vector(3 downto 0);
					muxSel				: in		std_logic;
					muxDIn				: in		std_logic_vector(1 downto 0);
					regDIn				: in		std_logic;
					regEn					: in		std_logic;
					regSet				: in		std_logic;
					regReset				: in		std_logic;
					fDOut					: out		std_logic;
					muxDOut				: out		std_logic;
					regDOut				: out		std_logic;
					shChnIn				: in		std_logic;
					shChnOut				: out		std_logic;
					cyChnIn				: in		std_logic;
					cyChnOut				: out		std_logic;
					cnfChnDIn			: in		std_logic;
					cnfChnDOut			: out		std_logic;
					cnfChnShiftEn		: in		std_logic;
					cnfChnLoadEn		: in		std_logic;
					cnfChnReadBackEn	: in		std_logic);
	end component;

	component IOBlock is
		port (	clk					: in		std_logic;
					nReset				: in		std_logic;
					-- Pad Connections
					padAIn				: in		std_logic;
					padAOut				: out		std_logic;
					padAOutEn			: out		std_logic;
					padBIn				: in		std_logic;
					padBOut				: out		std_logic;
					padBOutEn			: out		std_logic;
					-- Fabirc Connections
					linkCAIn				: in		std_logic;
					linkCBIn				: in		std_logic;
					linkCCIn				: in		std_logic;
					linkCDIn				: in		std_logic;
					linkR1In				: in		std_logic_vector(1 downto 0);
					linkR2In				: in		std_logic;
					linkR4In				: in		std_logic;
					linkPAOut			: out		std_logic;
					linkPBOut			: out		std_logic;
					linkIOOut			: out		std_logic_vector(4 downto 0);
					shChnIn				: in		std_logic;
					shChnOut				: out		std_logic;
					cyChnIn				: in		std_logic;
					cyChnOut				: out		std_logic;
					snapDIn				: in		std_logic;
					snapDOut				: out		std_logic;
					-- Routing Configuration
					rSelChnDIn			: in		std_logic;
					rSelChnDOut			: out		std_logic;
					rSelChnShiftEn		: in		std_logic;
					rCnfChnDIn			: in		std_logic;
					rCnfChnDOut			: out		std_logic;
					rCnfChnShiftEn		: in		std_logic;
					rCnfChnLoadEn		: in		std_logic;
					rCnfChnReadBackEn	: in		std_logic);
	end component;

	component Cluster is
		port (	clk					: in		std_logic;
					nReset				: in		std_logic;
					-- Chains
					shChnIn_N			: in		std_logic;
					shChnOut_N			: out		std_logic;
					cyChnIn_N			: in		std_logic;
					cyChnOut_N			: out		std_logic;
					shChnIn_S			: in		std_logic;
					shChnOut_S			: out		std_logic;
					cyChnIn_S			: in		std_logic;
					cyChnOut_S			: out		std_logic;
					shChnIn_E			: in		std_logic;
					shChnOut_E			: out		std_logic;
					cyChnIn_E			: in		std_logic;
					cyChnOut_E			: out		std_logic;
					shChnIn_W			: in		std_logic;
					shChnOut_W			: out		std_logic;
					cyChnIn_W			: in		std_logic;
					cyChnOut_W			: out		std_logic;
					-- Global Links
					linkGIn				: in		std_logic_vector(1 downto 0);
					-- Register Links
					linkR1In_N			: in		std_logic_vector(1 downto 0);
					linkR2In_N			: in		std_logic_vector(1 downto 0);
					linkR4In_N			: in		std_logic;
					linkROut_N			: out		std_logic_vector(1 downto 0);
					linkR1In_S			: in		std_logic_vector(1 downto 0);
					linkR2In_S			: in		std_logic_vector(1 downto 0);
					linkR4In_S			: in		std_logic;
					linkROut_S			: out		std_logic_vector(1 downto 0);
					linkR1In_E			: in		std_logic_vector(1 downto 0);
					linkR2In_E			: in		std_logic_vector(1 downto 0);
					linkR4In_E			: in		std_logic;
					linkROut_E			: out		std_logic_vector(1 downto 0);
					linkR1In_W			: in		std_logic_vector(1 downto 0);
					linkR2In_W			: in		std_logic_vector(1 downto 0);
					linkR4In_W			: in		std_logic;
					linkROut_W			: out		std_logic_vector(1 downto 0);
					-- Combinatorial Links
					linkCAIn_N			: in		std_logic;
					linkCBIn_N			: in		std_logic;
					linkCCIn_N			: in		std_logic;
					linkCDIn_N			: in		std_logic;
					linkCOut_N			: out		std_logic;
					linkCAIn_S			: in		std_logic;
					linkCBIn_S			: in		std_logic;
					linkCCIn_S			: in		std_logic;
					linkCDIn_S			: in		std_logic;
					linkCOut_S			: out		std_logic;
					linkCAIn_E			: in		std_logic;
					linkCBIn_E			: in		std_logic;
					linkCCIn_E			: in		std_logic;
					linkCDIn_E			: in		std_logic;
					linkCOut_E			: out		std_logic;
					linkCAIn_W			: in		std_logic;
					linkCBIn_W			: in		std_logic;
					linkCCIn_W			: in		std_logic;
					linkCDIn_W			: in		std_logic;
					linkCOut_W			: out		std_logic;
					-- Logic & Routing Configuration
					lSelChnDIn			: in		std_logic;
					lSelChnDOut			: out		std_logic;
					lSelChnShiftEn		: in		std_logic;
					lCnfChnDIn			: in		std_logic;
					lCnfChnDOut			: out		std_logic;
					lCnfChnShiftEn		: in		std_logic;
					lCnfChnLoadEn		: in		std_logic;
					lCnfChnReadBackEn	: in		std_logic;
					rSelChnDIn			: in		std_logic;
					rSelChnDOut			: out		std_logic;
					rSelChnShiftEn		: in		std_logic;
					rCnfChnDIn			: in		std_logic;
					rCnfChnDOut			: out		std_logic;
					rCnfChnShiftEn		: in		std_logic;
					rCnfChnLoadEn		: in		std_logic;
					rCnfChnReadBackEn	: in		std_logic);
	end component;

	component FPGA is
		generic(	NUM_COLS				: in		positive := 8;		-- X Dimension
					NUM_ROWS				: in		positive := 8);	-- Y Dimension
		port (	clk					: in		std_logic;
					nReset				: in		std_logic;
					-- Pads (2 in, 2 out per IOBlock)
					padIn_N				: in		std_logic_vector((NUM_COLS*2)-1 downto 0);
					padOut_N				: out		std_logic_vector((NUM_COLS*2)-1 downto 0);
					padOutEn_N			: out		std_logic_vector((NUM_COLS*2)-1 downto 0);
					padIn_S				: in		std_logic_vector((NUM_COLS*2)-1 downto 0);
					padOut_S				: out		std_logic_vector((NUM_COLS*2)-1 downto 0);
					padOutEn_S			: out		std_logic_vector((NUM_COLS*2)-1 downto 0);
					padIn_E				: in		std_logic_vector((NUM_ROWS*2)-1 downto 0);
					padOut_E				: out		std_logic_vector((NUM_ROWS*2)-1 downto 0);
					padOutEn_E			: out		std_logic_vector((NUM_ROWS*2)-1 downto 0);
					padIn_W				: in		std_logic_vector((NUM_ROWS*2)-1 downto 0);
					padOut_W				: out		std_logic_vector((NUM_ROWS*2)-1 downto 0);
					padOutEn_W			: out		std_logic_vector((NUM_ROWS*2)-1 downto 0);
					-- Global Inputs
					globalInputs		: in		std_logic_vector(1 downto 0);
					-- Snap Connections (1 in, 1out per IOBlock)
					snapDIn_N			: in		std_logic_vector(NUM_COLS-1 downto 0);
					snapDOut_N			: out		std_logic_vector(NUM_COLS-1 downto 0);
					snapDIn_S			: in		std_logic_vector(NUM_COLS-1 downto 0);
					snapDOut_S			: out		std_logic_vector(NUM_COLS-1 downto 0);
					snapDIn_E			: in		std_logic_vector(NUM_ROWS-1 downto 0);
					snapDOut_E			: out		std_logic_vector(NUM_ROWS-1 downto 0);
					snapDIn_W			: in		std_logic_vector(NUM_ROWS-1 downto 0);
					snapDOut_W			: out		std_logic_vector(NUM_ROWS-1 downto 0);
					-- Logic Configuration
					lSelChnDIn			: in		std_logic;
					lSelChnDOut			: out		std_logic;
					lSelChnShiftEn		: in		std_logic;
					lCnfChnDIn			: in		std_logic;
					lCnfChnDOut			: out		std_logic;
					lCnfChnShiftEn		: in		std_logic;
					lCnfChnLoadEn		: in		std_logic;
					lCnfChnReadBackEn	: in		std_logic;
					-- Routing Configuration
					rSelChnDIn			: in		std_logic;
					rSelChnDOut			: out		std_logic;
					rSelChnShiftEn		: in		std_logic;
					rCnfChnDIn			: in		std_logic;
					rCnfChnDOut			: out		std_logic;
					rCnfChnShiftEn		: in		std_logic;
					rCnfChnLoadEn		: in		std_logic;
					rCnfChnReadBackEn	: in		std_logic);
	end component;

end FPGAPkg;

package body FPGAPkg is

end FPGAPkg;