--------------------------------------------------------------------------------------------------------------- -- RISA Project -- Author: A.Greensted -- Module: -- Description: -- History: --------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library ConfigLib; use ConfigLib.ConfigPkg.all; library FPGALib; use FPGALib.FPGAPkg.all; entity Cluster is port ( clk : in std_logic; nReset : in std_logic; -- Chains shChnIn_N : in std_logic; shChnOut_N : out std_logic; cyChnIn_N : in std_logic; cyChnOut_N : out std_logic; shChnIn_S : in std_logic; shChnOut_S : out std_logic; cyChnIn_S : in std_logic; cyChnOut_S : out std_logic; shChnIn_E : in std_logic; shChnOut_E : out std_logic; cyChnIn_E : in std_logic; cyChnOut_E : out std_logic; shChnIn_W : in std_logic; shChnOut_W : out std_logic; cyChnIn_W : in std_logic; cyChnOut_W : out std_logic; -- Global Links linkGIn : in std_logic_vector(1 downto 0); -- Register Links linkR1In_N : in std_logic_vector(1 downto 0); linkR2In_N : in std_logic_vector(1 downto 0); linkR4In_N : in std_logic; linkROut_N : out std_logic_vector(1 downto 0); linkR1In_S : in std_logic_vector(1 downto 0); linkR2In_S : in std_logic_vector(1 downto 0); linkR4In_S : in std_logic; linkROut_S : out std_logic_vector(1 downto 0); linkR1In_E : in std_logic_vector(1 downto 0); linkR2In_E : in std_logic_vector(1 downto 0); linkR4In_E : in std_logic; linkROut_E : out std_logic_vector(1 downto 0); linkR1In_W : in std_logic_vector(1 downto 0); linkR2In_W : in std_logic_vector(1 downto 0); linkR4In_W : in std_logic; linkROut_W : out std_logic_vector(1 downto 0); -- Combinatorial Links linkCAIn_N : in std_logic; linkCBIn_N : in std_logic; linkCCIn_N : in std_logic; linkCDIn_N : in std_logic; linkCOut_N : out std_logic; linkCAIn_S : in std_logic; linkCBIn_S : in std_logic; linkCCIn_S : in std_logic; linkCDIn_S : in std_logic; linkCOut_S : out std_logic; linkCAIn_E : in std_logic; linkCBIn_E : in std_logic; linkCCIn_E : in std_logic; linkCDIn_E : in std_logic; linkCOut_E : out std_logic; linkCAIn_W : in std_logic; linkCBIn_W : in std_logic; linkCCIn_W : in std_logic; linkCDIn_W : in std_logic; linkCOut_W : out std_logic; -- Logic & Routing Configuration lSelChnDIn : in std_logic; lSelChnDOut : out std_logic; lSelChnShiftEn : in std_logic; lCnfChnDIn : in std_logic; lCnfChnDOut : out std_logic; lCnfChnShiftEn : in std_logic; lCnfChnLoadEn : in std_logic; lCnfChnReadBackEn : in std_logic; rSelChnDIn : in std_logic; rSelChnDOut : out std_logic; rSelChnShiftEn : in std_logic; rCnfChnDIn : in std_logic; rCnfChnDOut : out std_logic; rCnfChnShiftEn : in std_logic; rCnfChnLoadEn : in std_logic; rCnfChnReadBackEn : in std_logic); end Cluster; architecture General of Cluster is -- North Function Unit signal fuN_fDIn : std_logic; signal fuN_mode : std_logic_vector(1 downto 0); signal fuN_enable : std_logic; signal fuN_dIn : std_logic_vector(3 downto 0); signal fuN_muxSel : std_logic; signal fuN_muxDIn : std_logic_vector(1 downto 0); signal fuN_regDIn : std_logic; signal fuN_regEn : std_logic; signal fuN_regSet : std_logic; signal fuN_regReset : std_logic; signal fuN_fDOut : std_logic; signal fuN_muxDOut : std_logic; signal fuN_regDOut : std_logic; signal fuN_cnfChnDIn : std_logic; signal fuN_cnfChnDOut : std_logic; -- South Function Unit signal fuS_fDIn : std_logic; signal fuS_mode : std_logic_vector(1 downto 0); signal fuS_enable : std_logic; signal fuS_dIn : std_logic_vector(3 downto 0); signal fuS_muxSel : std_logic; signal fuS_muxDIn : std_logic_vector(1 downto 0); signal fuS_regDIn : std_logic; signal fuS_regEn : std_logic; signal fuS_regSet : std_logic; signal fuS_regReset : std_logic; signal fuS_fDOut : std_logic; signal fuS_muxDOut : std_logic; signal fuS_regDOut : std_logic; signal fuS_cnfChnDIn : std_logic; signal fuS_cnfChnDOut : std_logic; -- East Function Unit signal fuE_fDIn : std_logic; signal fuE_mode : std_logic_vector(1 downto 0); signal fuE_enable : std_logic; signal fuE_dIn : std_logic_vector(3 downto 0); signal fuE_muxSel : std_logic; signal fuE_muxDIn : std_logic_vector(1 downto 0); signal fuE_regDIn : std_logic; signal fuE_regEn : std_logic; signal fuE_regSet : std_logic; signal fuE_regReset : std_logic; signal fuE_fDOut : std_logic; signal fuE_muxDOut : std_logic; signal fuE_regDOut : std_logic; signal fuE_cnfChnDIn : std_logic; signal fuE_cnfChnDOut : std_logic; -- West Function Unit signal fuW_fDIn : std_logic; signal fuW_mode : std_logic_vector(1 downto 0); signal fuW_enable : std_logic; signal fuW_dIn : std_logic_vector(3 downto 0); signal fuW_muxSel : std_logic; signal fuW_muxDIn : std_logic_vector(1 downto 0); signal fuW_regDIn : std_logic; signal fuW_regEn : std_logic; signal fuW_regSet : std_logic; signal fuW_regReset : std_logic; signal fuW_fDOut : std_logic; signal fuW_muxDOut : std_logic; signal fuW_regDOut : std_logic; signal fuW_cnfChnDIn : std_logic; signal fuW_cnfChnDOut : std_logic; -- {{{ Function: selectRegInput impure function selectRegInput( connectionNum : std_logic_vector(4 downto 0) ) return std_logic is variable data : std_logic; begin -- Assign default value data := '0'; case connectionNum is when b"0_0000" => data := '0'; -- 0 when b"0_0001" => data := '1'; -- 1 when b"0_0010" => data := linkGIn(0); -- 2 when b"0_0011" => data := linkGIn(1); -- 3 when b"0_0100" => data := linkR1In_N(0); -- 4 when b"0_0101" => data := linkR1In_N(1); -- 5 when b"0_0110" => data := linkR1In_S(0); -- 6 when b"0_0111" => data := linkR1In_S(1); -- 7 when b"0_1000" => data := linkR1In_E(0); -- 8 when b"0_1001" => data := linkR1In_E(1); -- 9 when b"0_1010" => data := linkR1In_W(0); -- 10 when b"0_1011" => data := linkR1In_W(1); -- 11 when b"0_1100" => data := linkCAIn_N; -- 12 when b"0_1101" => data := linkCBIn_N; -- 13 when b"0_1110" => data := linkCAIn_S; -- 14 when b"0_1111" => data := linkCBIn_S; -- 15 when b"1_0000" => data := linkCAIn_E; -- 16 when b"1_0001" => data := linkCBIn_E; -- 17 when b"1_0010" => data := linkCAIn_W; -- 18 when b"1_0011" => data := linkCBIn_W; -- 19 when b"1_0100" => data := fuN_fDOut; -- 20 when b"1_0101" => data := fuN_muxDOut; -- 21 when b"1_0110" => data := fuN_regDOut; -- 22 when b"1_0111" => data := fuS_fDOut; -- 23 when b"1_1000" => data := fuS_muxDOut; -- 24 when b"1_1001" => data := fuS_regDOut; -- 25 when b"1_1010" => data := fuE_fDOut; -- 26 when b"1_1011" => data := fuE_muxDOut; -- 27 when b"1_1100" => data := fuE_regDOut; -- 28 when b"1_1101" => data := fuW_fDOut; -- 29 when b"1_1110" => data := fuW_muxDOut; -- 30 when b"1_1111" => data := fuW_regDOut; -- 31 when others => data := '0'; end case; return data; end function; -- }}} -- {{{ Function: selectCombInput impure function selectCombInput( connectionNum : std_logic_vector(4 downto 0); logicDir : FPGATYPE_LOGIC_DIR ) return std_logic is variable data : std_logic; begin -- Assign default value data := '0'; case connectionNum is when b"0_0000" => data := '0'; -- 0 when b"0_0001" => data := '1'; -- 1 when b"0_0010" => data := linkGIn(0); -- 2 when b"0_0011" => data := linkGIn(1); -- 3 when b"0_0100" => data := linkR1In_N(0); -- 4 when b"0_0101" => data := linkR1In_N(1); -- 5 when b"0_0110" => data := linkR2In_N(0); -- 6 when b"0_0111" => data := linkR2In_N(1); -- 7 when b"0_1000" => data := linkR4In_N; -- 8 when b"0_1001" => data := linkR1In_S(0); -- 9 when b"0_1010" => data := linkR1In_S(1); -- 10 when b"0_1011" => data := linkR2In_S(0); -- 11 when b"0_1100" => data := linkR2In_S(1); -- 12 when b"0_1101" => data := linkR4In_S; -- 13 when b"0_1110" => data := linkR1In_E(0); -- 14 when b"0_1111" => data := linkR1In_E(1); -- 15 when b"1_0000" => data := linkR2In_E(0); -- 16 when b"1_0001" => data := linkR2In_E(1); -- 17 when b"1_0010" => data := linkR4In_E; -- 18 when b"1_0011" => data := linkR1In_W(0); -- 19 when b"1_0100" => data := linkR1In_W(1); -- 20 when b"1_0101" => data := linkR2In_W(0); -- 21 when b"1_0110" => data := linkR2In_W(1); -- 22 when b"1_0111" => data := linkR4In_W; -- 23 when b"1_1000" => case logicDir is -- 24 when FPGA_NORTH => data := linkCAIn_N; when FPGA_SOUTH => data := linkCAIn_S; when FPGA_EAST => data := linkCAIn_E; when FPGA_WEST => data := linkCAIn_W; end case; when b"1_1001" => case logicDir is -- 25 when FPGA_NORTH => data := linkCBIn_N; when FPGA_SOUTH => data := linkCBIn_S; when FPGA_EAST => data := linkCBIn_E; when FPGA_WEST => data := linkCBIn_W; end case; when b"1_1010" => case logicDir is -- 26 when FPGA_NORTH => data := linkCCIn_N; when FPGA_SOUTH => data := linkCCIn_S; when FPGA_EAST => data := linkCCIn_E; when FPGA_WEST => data := linkCCIn_W; end case; when b"1_1011" => case logicDir is -- 27 when FPGA_NORTH => data := linkCDIn_N; when FPGA_SOUTH => data := linkCDIn_S; when FPGA_EAST => data := linkCDIn_E; when FPGA_WEST => data := linkCDIn_W; end case; when b"1_1100" => data := fuN_regDOut; -- 28 when b"1_1101" => data := fuS_regDOut; -- 29 when b"1_1110" => data := fuE_regDOut; -- 30 when b"1_1111" => data := fuW_regDOut; -- 31 when others => data := '0'; end case; return data; end function; -- }}} -- {{{ Function: selectRegOutput impure function selectRegOutput( connectionNum : std_logic_vector(1 downto 0) ) return std_logic is variable data : std_logic; begin -- Assign default value data := '0'; case connectionNum is when b"00" => data := fuN_regDOut; -- 0 when b"01" => data := fuS_regDOut; -- 1 when b"10" => data := fuE_regDOut; -- 2 when b"11" => data := fuW_regDOut; -- 3 when others => data := '0'; end case; return data; end function; -- }}} signal rCnfChn : std_logic_vector(320 downto 0); signal rCnfBit : std_logic_vector(319 downto 0); signal lCnfChnDInBP : std_logic; signal lCnfChnDOutBP : std_logic; signal lCnfChnShiftEnBP : std_logic; signal lCnfChnLoadEnBP : std_logic; signal lCnfChnReadBackEnBP : std_logic; signal rCnfChnDInBP : std_logic; signal rCnfChnDOutBP : std_logic; signal rCnfChnShiftEnBP : std_logic; signal rCnfChnLoadEnBP : std_logic; signal rCnfChnReadBackEnBP : std_logic; begin -- Select Units --------------------------------------------------------------------------------------------- -- Create Select units for Logic and Route Configuration chains ------------------------------------------------------------------------------------------------------------- ClusterLogicCnfSelectUnit : ConfigSelectUnit port map ( clk => clk, nReset => nReset, selChnDIn => lSelChnDIn, selChnDOut => lSelChnDOut, selChnShiftEn => lSelChnShiftEn, cnfChnDIn => lCnfChnDIn, cnfChnDOut => lCnfChnDOut, cnfChnShiftEn => lCnfChnShiftEn, cnfChnLoadEn => lCnfChnLoadEn, cnfChnReadBackEn => lCnfChnReadBackEn, cnfChnDInBP => lCnfChnDInBP, cnfChnDOutBP => lCnfChnDOutBP, cnfChnShiftEnBP => lCnfChnShiftEnBP, cnfChnLoadEnBP => lCnfChnLoadEnBP, cnfChnReadBackEnBP => lCnfChnReadBackEnBP); ClusterRouteCnfSelectUnit : ConfigSelectUnit port map ( clk => clk, nReset => nReset, selChnDIn => rSelChnDIn, selChnDOut => rSelChnDOut, selChnShiftEn => rSelChnShiftEn, cnfChnDIn => rCnfChnDIn, cnfChnDOut => rCnfChnDOut, cnfChnShiftEn => rCnfChnShiftEn, cnfChnLoadEn => rCnfChnLoadEn, cnfChnReadBackEn => rCnfChnReadBackEn, cnfChnDInBP => rCnfChnDInBP, cnfChnDOutBP => rCnfChnDOutBP, cnfChnShiftEnBP => rCnfChnShiftEnBP, cnfChnLoadEnBP => rCnfChnLoadEnBP, cnfChnReadBackEnBP => rCnfChnReadBackEnBP); -- RouteCnfBitGeneration ------------------------------------------------------------------------------------ -- Create configuration bits used for routing ------------------------------------------------------------------------------------------------------------- RouteCnfBitGeneration : for b in 0 to 319 generate begin ClusterCnfBit : ConfigurableBit port map ( clk => clk, nReset => nReset, cnfBit => rCnfBit(b), cnfChnDIn => rCnfChn(b), cnfChnDOut => rCnfChn(b+1), cnfChnShiftEn => rCnfChnShiftEnBP, cnfChnLoadEn => rCnfChnLoadEnBP, cnfChnReadBackEn => rCnfChnReadBackEnBP); end generate; -- Route Configuration rCnfChn(0) <= rCnfChnDOutBP; -- Connect rCnfChnDInBP <= rCnfChn(320); -- Logic Configuration (->N->S->E->W->) fuN_cnfChnDIn <= lCnfChnDOutBP; fuS_cnfChnDIn <= fuN_cnfChnDOut; fuE_cnfChnDIn <= fuS_cnfChnDOut; fuW_cnfChnDIn <= fuE_cnfChnDOut; lCnfChnDInBP <= fuW_cnfChnDOut; -- North Function Unit -------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- FU_North : FunctionUnit port map ( clk => clk, nReset => nReset, fDIn => fuN_fDIn, mode => fuN_mode, enable => fuN_enable, dIn => fuN_dIn, muxSel => fuN_muxSel, muxDIn => fuN_muxDIn, regDIn => fuN_regDIn, regEn => fuN_regEn, regSet => fuN_regSet, regReset => fuN_regReset, fDOut => fuN_fDOut, muxDOut => fuN_muxDOut, regDOut => fuN_regDOut, shChnIn => shChnIn_N, shChnOut => shChnOut_N, cyChnIn => cyChnIn_N, cyChnOut => cyChnOut_N, cnfChnDIn => fuN_cnfChnDIn, cnfChnDOut => fuN_cnfChnDOut, cnfChnShiftEn => lCnfChnShiftEnBP, cnfChnLoadEn => lCnfChnLoadEnBP, cnfChnReadBackEn => lCnfChnReadBackEnBP); -- South Function Unit -------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- FU_South : FunctionUnit port map ( clk => clk, nReset => nReset, fDIn => fuS_fDIn, mode => fuS_mode, enable => fuS_enable, dIn => fuS_dIn, muxSel => fuS_muxSel, muxDIn => fuS_muxDIn, regDIn => fuS_regDIn, regEn => fuS_regEn, regSet => fuS_regSet, regReset => fuS_regReset, fDOut => fuS_fDOut, muxDOut => fuS_muxDOut, regDOut => fuS_regDOut, shChnIn => shChnIn_S, shChnOut => shChnOut_S, cyChnIn => cyChnIn_S, cyChnOut => cyChnOut_S, cnfChnDIn => fuS_cnfChnDIn, cnfChnDOut => fuS_cnfChnDOut, cnfChnShiftEn => lCnfChnShiftEnBP, cnfChnLoadEn => lCnfChnLoadEnBP, cnfChnReadBackEn => lCnfChnReadBackEnBP); -- East Function Unit --------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- FU_East : FunctionUnit port map ( clk => clk, nReset => nReset, fDIn => fuE_fDIn, mode => fuE_mode, enable => fuE_enable, dIn => fuE_dIn, muxSel => fuE_muxSel, muxDIn => fuE_muxDIn, regDIn => fuE_regDIn, regEn => fuE_regEn, regSet => fuE_regSet, regReset => fuE_regReset, fDOut => fuE_fDOut, muxDOut => fuE_muxDOut, regDOut => fuE_regDOut, shChnIn => shChnIn_E, shChnOut => shChnOut_E, cyChnIn => cyChnIn_E, cyChnOut => cyChnOut_E, cnfChnDIn => fuE_cnfChnDIn, cnfChnDOut => fuE_cnfChnDOut, cnfChnShiftEn => lCnfChnShiftEnBP, cnfChnLoadEn => lCnfChnLoadEnBP, cnfChnReadBackEn => lCnfChnReadBackEnBP); -- West Function Unit --------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- FU_West : FunctionUnit port map ( clk => clk, nReset => nReset, fDIn => fuW_fDIn, mode => fuW_mode, enable => fuW_enable, dIn => fuW_dIn, muxSel => fuW_muxSel, muxDIn => fuW_muxDIn, regDIn => fuW_regDIn, regEn => fuW_regEn, regSet => fuW_regSet, regReset => fuW_regReset, fDOut => fuW_fDOut, muxDOut => fuW_muxDOut, regDOut => fuW_regDOut, shChnIn => shChnIn_W, shChnOut => shChnOut_W, cyChnIn => cyChnIn_W, cyChnOut => cyChnOut_W, cnfChnDIn => fuW_cnfChnDIn, cnfChnDOut => fuW_cnfChnDOut, cnfChnShiftEn => lCnfChnShiftEnBP, cnfChnLoadEn => lCnfChnLoadEnBP, cnfChnReadBackEn => lCnfChnReadBackEnBP); SwitchBox : process( fuE_fDOut, fuE_muxDOut, fuE_regDOut, fuN_fDOut, fuN_muxDOut, fuN_regDOut, fuS_fDOut, fuS_muxDOut, fuS_regDOut, fuW_fDOut, fuW_muxDOut, fuW_regDOut, linkCAIn_E, linkCAIn_N, linkCAIn_S, linkCAIn_W, linkCBIn_E, linkCBIn_N, linkCBIn_S, linkCBIn_W, linkCCIn_E, linkCCIn_N, linkCCIn_S, linkCCIn_W, linkCDIn_E, linkCDIn_N, linkCDIn_S, linkCDIn_W, linkGIn, linkR1In_E, linkR1In_N, linkR1In_S, linkR1In_W, linkR2In_E, linkR2In_N, linkR2In_S, linkR2In_W, linkR4In_E, linkR4In_N, linkR4In_S, linkR4In_W, rCnfBit) begin -- North Function Unit fuN_fDIn <= selectRegInput( rCnfBit(4 downto 0)); fuN_mode(0) <= selectRegInput( rCnfBit(9 downto 5)); fuN_mode(1) <= selectRegInput( rCnfBit(14 downto 10)); fuN_enable <= selectRegInput( rCnfBit(19 downto 15)); fuN_dIn(0) <= selectCombInput( rCnfBit(24 downto 20), FPGA_NORTH); fuN_dIn(1) <= selectCombInput( rCnfBit(29 downto 25), FPGA_NORTH); fuN_dIn(2) <= selectCombInput( rCnfBit(34 downto 30), FPGA_NORTH); fuN_dIn(3) <= selectCombInput( rCnfBit(39 downto 35), FPGA_NORTH); fuN_muxSel <= selectCombInput( rCnfBit(44 downto 40), FPGA_NORTH); fuN_muxDIn(0) <= selectCombInput( rCnfBit(49 downto 45), FPGA_NORTH); fuN_muxDIn(1) <= selectCombInput( rCnfBit(54 downto 50), FPGA_NORTH); fuN_regDIn <= selectRegInput( rCnfBit(59 downto 55)); fuN_regEn <= selectRegInput( rCnfBit(64 downto 60)); fuN_regSet <= selectRegInput( rCnfBit(69 downto 65)); fuN_regReset <= selectRegInput( rCnfBit(74 downto 70)); linkROut_N(0) <= selectRegOutput( rCnfBit(76 downto 75)); linkROut_N(1) <= selectRegOutput( rCnfBit(78 downto 77)); if (rCnfBit(79)='1') then linkCOut_N <= fuN_muxDOut; else linkCOut_N <= fuN_fDOut; end if; -- South Function Unit fuS_fDIn <= selectRegInput( rCnfBit(84 downto 80)); fuS_mode(0) <= selectRegInput( rCnfBit(89 downto 85)); fuS_mode(1) <= selectRegInput( rCnfBit(94 downto 90)); fuS_enable <= selectRegInput( rCnfBit(99 downto 95)); fuS_dIn(0) <= selectCombInput( rCnfBit(104 downto 100), FPGA_SOUTH); fuS_dIn(1) <= selectCombInput( rCnfBit(109 downto 105), FPGA_SOUTH); fuS_dIn(2) <= selectCombInput( rCnfBit(114 downto 110), FPGA_SOUTH); fuS_dIn(3) <= selectCombInput( rCnfBit(119 downto 115), FPGA_SOUTH); fuS_muxSel <= selectCombInput( rCnfBit(124 downto 120), FPGA_SOUTH); fuS_muxDIn(0) <= selectCombInput( rCnfBit(129 downto 125), FPGA_SOUTH); fuS_muxDIn(1) <= selectCombInput( rCnfBit(134 downto 130), FPGA_SOUTH); fuS_regDIn <= selectRegInput( rCnfBit(139 downto 135)); fuS_regEn <= selectRegInput( rCnfBit(144 downto 140)); fuS_regSet <= selectRegInput( rCnfBit(149 downto 145)); fuS_regReset <= selectRegInput( rCnfBit(154 downto 150)); linkROut_S(0) <= selectRegOutput( rCnfBit(156 downto 155)); linkROut_S(1) <= selectRegOutput( rCnfBit(158 downto 157)); if (rCnfBit(159)='1') then linkCOut_S <= fuS_muxDOut; else linkCOut_S <= fuS_fDOut; end if; -- East Function Unit fuE_fDIn <= selectRegInput( rCnfBit(164 downto 160)); fuE_mode(0) <= selectRegInput( rCnfBit(169 downto 165)); fuE_mode(1) <= selectRegInput( rCnfBit(174 downto 170)); fuE_enable <= selectRegInput( rCnfBit(179 downto 175)); fuE_dIn(0) <= selectCombInput( rCnfBit(184 downto 180), FPGA_EAST); fuE_dIn(1) <= selectCombInput( rCnfBit(189 downto 185), FPGA_EAST); fuE_dIn(2) <= selectCombInput( rCnfBit(194 downto 190), FPGA_EAST); fuE_dIn(3) <= selectCombInput( rCnfBit(199 downto 195), FPGA_EAST); fuE_muxSel <= selectCombInput( rCnfBit(204 downto 200), FPGA_EAST); fuE_muxDIn(0) <= selectCombInput( rCnfBit(209 downto 205), FPGA_EAST); fuE_muxDIn(1) <= selectCombInput( rCnfBit(214 downto 210), FPGA_EAST); fuE_regDIn <= selectRegInput( rCnfBit(219 downto 215)); fuE_regEn <= selectRegInput( rCnfBit(224 downto 220)); fuE_regSet <= selectRegInput( rCnfBit(229 downto 225)); fuE_regReset <= selectRegInput( rCnfBit(234 downto 230)); linkROut_E(0) <= selectRegOutput( rCnfBit(236 downto 235)); linkROut_E(1) <= selectRegOutput( rCnfBit(238 downto 237)); if (rCnfBit(239)='1') then linkCOut_E <= fuE_muxDOut; else linkCOut_E <= fuE_fDOut; end if; -- West Function Unit fuW_fDIn <= selectRegInput( rCnfBit(244 downto 240)); fuW_mode(0) <= selectRegInput( rCnfBit(249 downto 245)); fuW_mode(1) <= selectRegInput( rCnfBit(254 downto 250)); fuW_enable <= selectRegInput( rCnfBit(259 downto 255)); fuW_dIn(0) <= selectCombInput( rCnfBit(264 downto 260), FPGA_WEST); fuW_dIn(1) <= selectCombInput( rCnfBit(269 downto 265), FPGA_WEST); fuW_dIn(2) <= selectCombInput( rCnfBit(274 downto 270), FPGA_WEST); fuW_dIn(3) <= selectCombInput( rCnfBit(279 downto 275), FPGA_WEST); fuW_muxSel <= selectCombInput( rCnfBit(284 downto 280), FPGA_WEST); fuW_muxDIn(0) <= selectCombInput( rCnfBit(289 downto 285), FPGA_WEST); fuW_muxDIn(1) <= selectCombInput( rCnfBit(294 downto 290), FPGA_WEST); fuW_regDIn <= selectRegInput( rCnfBit(299 downto 295)); fuW_regEn <= selectRegInput( rCnfBit(304 downto 300)); fuW_regSet <= selectRegInput( rCnfBit(309 downto 305)); fuW_regReset <= selectRegInput( rCnfBit(314 downto 310)); linkROut_W(0) <= selectRegOutput( rCnfBit(316 downto 315)); linkROut_W(1) <= selectRegOutput( rCnfBit(318 downto 317)); if (rCnfBit(319)='1') then linkCOut_W <= fuW_muxDOut; else linkCOut_W <= fuW_fDOut; end if; end process; end General; --with rCnfBit(316 downto 315) select linkROut_W(0) <= fuN_regDOut when b"00", fuS_regDOut when b"01", fuE_regDOut when b"10", fuW_regDOut when b"11", '0' when others; --with rCnfBit(318 downto 317) select linkROut_W(1) <= fuN_regDOut when b"00", fuS_regDOut when b"01", fuE_regDOut when b"10", fuW_regDOut when b"11", '0' when others; --with rCnfBit ( downto ) select XXX <= '0' when b"0_0000", '1' when b"0_0001", linkGIn(0) when b"0_0010", linkGIn(1) when b"0_0011", linkR1In_N(0) when b"0_0100", linkR1In_N(1) when b"0_0101", linkR2In_N(0) when b"0_0110", linkR2In_N(1) when b"0_0111", linkR4In_N when b"0_1000", linkR1In_S(0) when b"0_1001", linkR1In_S(1) when b"0_1010", linkR2In_S(0) when b"0_1011", linkR2In_S(1) when b"0_1100", linkR4In_S when b"0_1101", linkR1In_E(0) when b"0_1110", linkR1In_E(1) when b"0_1111", linkR2In_E(0) when b"1_0000", linkR2In_E(1) when b"1_0001", linkR4In_E when b"1_0010", linkR1In_W(0) when b"1_0011", linkR1In_W(1) when b"1_0100", linkR2In_W(0) when b"1_0101", linkR2In_W(1) when b"1_0110", linkR4In_W when b"1_0111", linkCAIn_N when b"1_1000", linkCBIn_N when b"1_1001", linkCCIn_N when b"1_1010", linkCDIn_N when b"1_1011", fuN_regDOut when b"1_1100", fuS_regDOut when b"1_1101", fuE_regDOut when b"1_1110", fuW_regDOut when b"1_1111", '0' when others;