RISA Project

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This page contains resources for the Reconfigurable Integrated System Array (RISA) architecture.

• Introduction
• Source Code

• Introduction

The RISA architecture is a new form of reconfigurable electronic device developed for implementing biologically inspired systems. The architecture includes both hardware and software reconfigurable parts. The diagram below illustrates the RISA design.

• Source Code

SNAP

Unit				Schematic	Source code	Description
	SnapPkg				SnapPkg.vhdl	Snap Package (constants and function)
	Snap			Snap.svg	Snap.vhdl	The Top level SNAP module
		ALU		ALU.svg	ALU.vhdl	The arithmetic logic unit.
		Counter		Counter.svg	Counter.vhdl	16-bit Counter Unit
		FabricCAP			FabricCAP.vhdl	FPGA Fabric Configurartion Access Port
		FabricIOPort			FabricIOPort.vhdl	General purpose IO link to FPGA fabric
		FlagsRegisters			FlagsRegisters.vhdl	The register holding SNAP status flags
		InterruptController			InterruptController.vhdl	Registers for interrupt control
		IOPort			IOPort.vhdl	General Purpose IO registers
		ProgramCounter			ProgramCounter.vhdl	The program counter register
		SnapLink			SnapLink.vhdl	Inter-SNAP comms module
			SnapLinkTx		SnapLinkTx.vhdl	SNAPLink Tx sub-module
			SnapLinkRx		SnapLinkRx.vhdl	SNAPLink rx sub-module
		SystemUART			SystemUART.vhdl	Serial UART module
			SystemUARTTx		SystemUARTTx.vhdl	SystemUART Tx sub-module
			SystemUARTRx		SystemUARTRx.vhdl	SystemUART Rx sub-module
		WatchDogTimer		WatchDogTimer.svg	WatchDogTimer.vhdl	16 bit Watch Dog Timer Module
		WorkingRegisters			WorkingRegisters.vhdl	32x16-bit Working register file

FPGA

Unit					Schematic	Source code	Description
	FPGAPkg					FPGAPkg.vhdl	FPGA Package (constants and function)
	FPGA					FPGA.vhdl	The Top level FPGA module
		Cluster			Cluster.svg	Cluster.vhdl	Routing and Logic.
			FunctionUnit		FunctionUnit.svg	FunctionUnit.vhdl	Main configurable logic section.
				FunctionGenerator	FunctionGenerator.svg	FunctionGenerator.vhdl	Function Generator (LUT).
			IOBlock		IOBlock.svg	IOBlock.vhdl	Input/Output Block

Config

Unit			Schematic	Source code	Description
	ConfigPkg			ConfigPkg.vhdl	FPGA Package (constants and function)
	ConfigAccessPort		ConfigAccessPort.svg	ConfigAccessPort.vhdl	Chip Config Access Port
		ConfigAccessPort_CAP		ConfigAccessPort_CAP.vhdl	CAP, external domain
		ConfigAccessPort_CNF		ConfigAccessPort_CNF.vhdl	CAP, intenral domain
	ConfigArbiter		ConfigArbiter.svg	ConfigArbiter.vhdl	Configuration control
	ConfigSelectUnit		ConfigSelectUnit.svg	ConfigSelectUnit.vhdl	Sub Chain selection unit
	ConfigurableBit		ConfigurableBit.svg	ConfigurableBit.vhdl	Configurable bit
	ConfigurableMemory		ConfigurableMemory.svg	ConfigurableMemory.vhdl	Configurable memory
	ConfigurableRegister		ConfigurableRegister.svg	ConfigurableRegister.vhdl	Configurable register
	ConfigurableSRRegister			ConfigurableSRRegister.vhdl	Configurable register