VHDL
A basic crib sheet of various parts of VHDL. Those bits that are hard to
remember, or just easier to cut and paste than to type out.
• Type Conversion
std_logic_vector ↔ integer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
signal slv : std_logic_vector(3 downto 0);
signal int : integer;
int <= to_integer(unsigned(slv));
slv <= std_logic_vector(to_unsigned(int, 4));
• VHDL Cases
case sel is
when b"000" => result := input(0);
when b"001" => result := input(1);
when b"010" => result := input(2);
when b"011" => result := input(3);
when b"100" => result := input(4);
when b"101" => result := input(5);
when b"110" => result := input(6);
when b"111" => result := input(7);
when others => assert false report "Bad sel value" severity failure;
end case;
• Random Numbers
When simulating a VHDL module within a testbench, it can be useful to have
some form of random number source. The uniform function in the
math_real library can be used to produce (pseudo) random numbers.
The example below shows how to use the function. Variables s1 and s2 are used
internally.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
variable s1 : positive := 234;
variable s2 : positive := 567;
variable randNum : real;
variable slv : std_logic_vector(7 downto 0);
uniform(s1, s2, randNum);
randNum := randNum * 256.0;
randNum := floor(randNum);
slv := std_logic_vector(to_unsigned(integer(randNum), 8));
slv := std_logic_vector(to_unsigned(integer(floor(randnum * 256.0)), 8));
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