VCC VW-300
The VCC VW-300 is a FPGA development board. It has an on board XCV300 Xilinx
FPGA. This page contains some details for using the board.
• FPGA Pins
The following tables contain the FPGA pin numbers for connections to the board's various
peripherals.
| LED Pins | Description |
| L3 | LED0 |
| L2 | LED1 |
| M2 | LED2 |
| M1 | LED3 |
| N3 | LED4 |
| N4 | LED5 |
| N2 | LED6 |
| AC13 | LED7 (Board Edge) |
| | |
| Clock Pins | Description |
| AE13 | GCLK0 (33MHz) |
| AF14 | GCLK1 (50MHz) |
| B14 | GCLK2 |
| D14 | GCLK3 |
| | |
| RS232 Pins | Description |
| AE21 | RXD |
| AC19 | TXD |
| | |
| DIL Switch Pins | Description |
| AC5 | SW1 (Board Edge) |
| AD4 | SW2 |
| AE3 | SW3 |
| AD5 | SW4 |
| AC6 | SW5 |
| AF3 | SW6 |
| AF4 | SW7 |
| AC7 | SW8 |
|
| Push Buttons Pins | Description |
| AA4 | PB1 (Board Edge) |
| AB3 | PB1 |
| AD1 | PB2 |
| AB4 | PB3 |
| | |
| Display Pins | Description |
| W3 | D0_LOAD_DISP (D0) |
| AA1 | D1_DISP (D1) |
| AC1 | D2_DISP (D2) |
| AA3 | D3_DISP (D3) |
| AB2 | D4_DISP (D4) |
| AA2 | D5_SDATA_DISP (D5) |
| W4 | D6_NC_DISP (D6) |
| Y2 | D7_SCLK_DISP (D7) |
| V1 | A0_DISP (A0) |
| T3 | A1_DISP (A1) |
| T2 | A2_RESET_DISP (A2) |
| R1 | A3_CLKIO_DISP (A3) |
| P1 | A4_DISP (A4) |
| P3 | CLK_SEL_DISP (CLS) |
| R2 | CLK_DISP (CLK) |
| U2 | WRN_DISP (WR) |
| T4 | CEN_DISP (CE) |
| Y1 | RDN_DISP (RD) |
| V2 | RSTN_DISP (RST) |
| U3 | FL_DISP (FL) |
|
• Data Sheets
Below are a set of links to documents related to the board. Included
are datasheets for the various components found on the board, board schematics and some articles.
Data Sheets
Schematics
Articles
• Test Designs
Below are a set of links to test designs, these could be used as references, or just to
check that the hardware is working.
• JTAG Configuration Chain
The FPGA on the VCC board can be configured via a JTAG chain. The image below shows the devices on the
chain, the Virtex FPGA and a Xilinx CPLD.
It is possible, and probably easier, to use impact from the command line. By
using batch files, you can store a set of impact commands. These batch files
are then run by using impact's -batch flag, as shown below. The batch file in
this case being called boardID.batch.
> impact -batch boardID.batch
The batch file shown below will display the contents of the board's JTAG chain and is useful
for checking that the cable is all connected up OK.
• File: boardID.batch
setMode -bs
setCable -port lpt2
identify
info
quit
This second batch file can be used to configure the FPGA. It reads a bit
file called bitFile.bit. You will also need the bsd file
xc9536.bsd for the CPLD. This can be found within the files installed with ISE.
• File: program.batch
setMode -bs
setCable -port lpt2
addDevice -p 1 -file "bitFile.bit"
addDevice -p 2 -part "xc9536.bsd"
program -p 1
quit
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