Modelsim

• A Simple Batch Files
• TCL Tricks

• A simple Batch File

First, use vlib to create a design library called work. This is the default design library name

vlib work

Compile the VHDL source files using the vcom command. The meaning of the used vcom flags are:

• -93 Enable support VHDL 1076-1993
• -pedanticerrors Enforce strict language checks
• -lint Perform lint-style checks
• +acc=v Enable access to vairables
• -work Place into library work

vcom -93 -pedanticerrors -lint +acc=v -work work Node.vhdl

Compile the TestBench VHDL source files then simulate.

• -t 1ps Set the time resolution to 1 ps

vcom -93 Node_TB.vhdl
vsim -t 1ps -lib work Node_TB

Configure the waveform window. Also undock the window from the main GUI.

configure wave -gridperiod 5000;
configure wave -griddelta 50
configure wave -signalnamewidth 1

view wave -undock

Add a number of waveforms to the wave window.

add wave -divider "Top Signals"
add wave -height 20 -color cornflowerBlue    clk
add wave -height 20 -color greenYellow       reset

Run the simulation for 5 us.

run 5 us

• TCL Tricks

If you add a wave for an array, then modelsim will show all the entries.

add wave -height 20 -color orange -expand      array

You can use a bit of TCL to achieve a simlar thing. The first line looks up (using examine) a constant value ARRAY_LENGTH. This is set to the variable arrayLength. A for loop is then used to add a set of individual waves, one for each element. This is quite a flexible approach.

set arrayLength [examine UUT/ARRAY_LENGTH]

for {set c [expr $arrayLength -1]} {$c>=0} {incr c -1} {
	add wave -height 20 -color orange -hex      array($c)
}