library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;

entity LCDDriver_TB is
end LCDDriver_TB;

architecture TestBench of LCDDriver_TB is

	component LCDDriver
		generic ( tickNum		: positive := 320);
		port (	clk			: in		std_logic;
					reset			: in		std_logic;
					dIn			: in		std_logic_vector(7 downto 0);
					charNum		: in		std_logic_vector(5 downto 0);
					wEn			: in		std_logic;
					lcdData		: out		std_logic_vector(7 downto 0);
					lcdRS			: out		std_logic;
					lcdRW			: out		std_logic;
					lcdE			: out		std_logic);
	end component;

	signal clk		: std_logic;
	signal reset	: std_logic;
	signal dIn		: std_logic_vector(7 downto 0);
	signal charNum	: std_logic_vector(5 downto 0);
	signal wEn		: std_logic;
	signal lcdData	: std_logic_vector(7 downto 0);
	signal lcdRS	: std_logic;
	signal lcdRW	: std_logic;
	signal lcdE		: std_logic;

begin

MainClk : process
begin
	clk <= '1';
	wait for 15.625 ns;		-- 32 MHz
	clk <= '0';
	wait for 15.625 ns;
end process;

Driver : LCDDriver
generic map(tickNum	=> 320)
port map(	clk		=> clk,
				reset		=> reset,
				dIn		=> dIn,
				charNum	=> charNum,
				wEn		=> wEn,
				lcdData	=> lcdData,
				lcdRS		=> lcdRS,
				lcdRW		=> lcdRW,
				lcdE		=> lcdE);

TB : process
begin

	reset		<= '1';	
	dIn		<= (others => '0');
	charNum	<= (others => '0');
	wEn		<= '0';

	wait until (clk'event and clk='1');
	wait until (clk'event and clk='1');

	reset <= '0';	

	wait;

end process;

end TestBench;